中英文精簡版有源晶振參數(shù)詞匯表
來源：http://m.techzozo.com 作者：金洛鑫電子 2018年12月19
關(guān)于有源晶振的參數(shù)規(guī)格，大部分采購可能只認(rèn)識比較主要的封裝尺寸，類型，頻率，精度，電源電壓之類的，但其實(shí)振蕩器詳細(xì)的參數(shù)并止這些。而是多達(dá)十幾種甚至是二十幾種，VCXO是壓控晶體振蕩器的英文簡稱，具有電壓控制性能，因此被命名為壓控晶振，適合用到無線通信，飛機(jī)船舶，工業(yè)儀器儀表，軍用，全球?qū)Ш蕉ㄎ幌到y(tǒng)，智能手機(jī)等產(chǎn)品。以下是VCXO晶振相關(guān)的詳細(xì)的參數(shù)及其含義。
PPM：“百萬分率”的縮寫，一種用于指定允許值的計(jì)算方法，晶體或石英晶體振蕩器的頻率偏差。也可以被視為“ppm”。
相位噪聲：一個(gè)相位調(diào)制邊帶的功率密度與總信號之比。目錄中的所有相位噪聲數(shù)據(jù)歸一化為一赫茲等效帶寬。
負(fù)載（扇出）：振蕩器驅(qū)動其他設(shè)備的容量。 TTL器件以可驅(qū)動的門數(shù)指定;即10個(gè)TTL門。 CMOS輸出以pF指定;即15 pF或50 pF負(fù)載。
啟用/禁用：啟用/禁用引腳類似于開/關(guān)開關(guān)。啟用/禁用時(shí)為低電平或邏輯0會導(dǎo)致設(shè)備不振蕩。使能/禁止引腳上的“高電平”或邏輯1允許單元正常工作（使能），產(chǎn)生指定的輸出。
偏差：數(shù)量與其名義價(jià)值的差異。出于目的，頻率與標(biāo)稱頻率或指定頻率不同的量。
下降時(shí)間：信號從邏輯'1'變?yōu)檫壿?#39;0'所需的時(shí)間。
頻率范圍：晶振可以制造的頻率范圍，對規(guī)格的影響最小。
線性度：偏離控制電壓與輸出頻率的直線關(guān)系。
振蕩器：在其輸出端產(chǎn)生特定頻率的交流電的電路或設(shè)備。
老化：振蕩器輸出頻率的系統(tǒng)平均變化僅作為時(shí)間的函數(shù)。老齡化不包括環(huán)境變化的影響。
可移動性：壓控晶體振蕩器的頻移是控制電壓的函數(shù)。
上升時(shí)間：信號從邏輯'0'變?yōu)檫壿?#39;1'所需的時(shí)間。
穩(wěn)定性：由溫度變化引起的振蕩器頻率的變化，以所需的振蕩器頻率為參考。
啟動：從瞬時(shí)電壓施加到振蕩器的時(shí)間，直到振蕩器輸出穩(wěn)定。
預(yù)熱：振蕩器頻率在幾小時(shí)后穩(wěn)定在給定的頻率容差范圍內(nèi)所需的時(shí)間。
三態(tài)：三態(tài)選項(xiàng)類似于啟用/禁用。當(dāng)pin1上有一個(gè)“邏輯1”（例如5 Vdc）時(shí)，該單元正常工作“啟用”，產(chǎn)生指定的輸出（例如TTL）。當(dāng)引腳被禁止時(shí)，“邏輯0”（ex 0 Vdc）進(jìn)入高阻抗或三態(tài)模式。三態(tài)模式允許客戶從電路中移除石英振蕩器而無需將其物理移除。用于調(diào)整，測試或解決他們的電路板問題。
對稱性：信號處于邏輯高電平的每個(gè)周期的百分比。該參數(shù)在指定的電壓閾值或輸出波形幅度的百分比下測量。
英文版：
Aging: A systematic average change of an oscillator’s output frequency as a function only of time. Aging does not include effects of changing environments.
Deviation: The amount by which a quantity differs from its nominal value. For purposes, the amount by which a frequency differs from the nominal or specified frequency.
Enable/Disable: The enable/disable pin is similar to an on/off switch. A low or logic 0 on the enable/disable causes the unit not to oscillate. A “high” or logic 1 on the enable/disable pin allows the unit to work as normal (enabled) producing the specified output.
Fall Time: the time required for a signal to go from Logic ‘1’ to logic ‘0’.
Frequency Range: The range of frequencies over which an oscillator can be fabricated with minimal impact on specifications.
Linearity: The departure from a straight line relationship of control voltage to output frequency.
Oscillator: A circuit or device that produces an alternating current of a specific frequency at its output terminals.
Phase Noise: The ratio of the power density of one phase modulation sideband to the total signal. All phase noise data in the catalog are normalized to a one Hertz equivalent bandwidth.
Load (Fan out): The capacity of the oscillator to drive other devices. TTL devices are specified in the number of gates that can be driven; i.e., 10 TTL gates. CMOS outputs are specified in pF; i.e. 15 pF or 50 pF loads.
PPM: The abbreviation for “Parts Per Million,” a method of calculation used to specify the permissible
frequency deviation of a crystal or oscillator. May also be seen as “ppm”.
Pullability: The frequency shift of a VCXO as a function of control voltage.
Rise Time: The time required for a signal to go from Logic ‘0’ to logic ‘1’.
Stability: The change in oscillator frequency, referenced to the desired oscillator frequency, caused by temperature change.
Start-Up: The period from the instant voltage is applied to the oscillator until the oscillator output is stabilized.
Symmetry: The percentage of each period that a signal is in logic high. This parameter is measured at a specified voltage threshold or at a percentage of the output waveform amplitude.
Tri-state: The tri-state option is similar to the Enable/Disable. When you have a “logic 1” (ex 5 Vdc) on pin1,the unit works as normal “enabled” producing the specified output (ex TTL). When the pin is disabled, “logic 0” (ex 0 Vdc) it goes into high impedance or tristate mode. The tristate mode allows the customer to remove the oscillator from their circuit without physically removing it. Useful for tuning, testing or trouble shooting their board.
Warm-Up: The time required for an oscillator’s frequency to settle to within a given tolerance of the frequency several hours later.
PPM：“百萬分率”的縮寫，一種用于指定允許值的計(jì)算方法，晶體或石英晶體振蕩器的頻率偏差。也可以被視為“ppm”。
相位噪聲：一個(gè)相位調(diào)制邊帶的功率密度與總信號之比。目錄中的所有相位噪聲數(shù)據(jù)歸一化為一赫茲等效帶寬。
負(fù)載（扇出）：振蕩器驅(qū)動其他設(shè)備的容量。 TTL器件以可驅(qū)動的門數(shù)指定;即10個(gè)TTL門。 CMOS輸出以pF指定;即15 pF或50 pF負(fù)載。
啟用/禁用：啟用/禁用引腳類似于開/關(guān)開關(guān)。啟用/禁用時(shí)為低電平或邏輯0會導(dǎo)致設(shè)備不振蕩。使能/禁止引腳上的“高電平”或邏輯1允許單元正常工作（使能），產(chǎn)生指定的輸出。
偏差：數(shù)量與其名義價(jià)值的差異。出于目的，頻率與標(biāo)稱頻率或指定頻率不同的量。
下降時(shí)間：信號從邏輯'1'變?yōu)檫壿?#39;0'所需的時(shí)間。
頻率范圍：晶振可以制造的頻率范圍，對規(guī)格的影響最小。
線性度：偏離控制電壓與輸出頻率的直線關(guān)系。
振蕩器：在其輸出端產(chǎn)生特定頻率的交流電的電路或設(shè)備。
老化：振蕩器輸出頻率的系統(tǒng)平均變化僅作為時(shí)間的函數(shù)。老齡化不包括環(huán)境變化的影響。
可移動性：壓控晶體振蕩器的頻移是控制電壓的函數(shù)。
上升時(shí)間：信號從邏輯'0'變?yōu)檫壿?#39;1'所需的時(shí)間。
穩(wěn)定性：由溫度變化引起的振蕩器頻率的變化，以所需的振蕩器頻率為參考。
啟動：從瞬時(shí)電壓施加到振蕩器的時(shí)間，直到振蕩器輸出穩(wěn)定。
預(yù)熱：振蕩器頻率在幾小時(shí)后穩(wěn)定在給定的頻率容差范圍內(nèi)所需的時(shí)間。
三態(tài)：三態(tài)選項(xiàng)類似于啟用/禁用。當(dāng)pin1上有一個(gè)“邏輯1”（例如5 Vdc）時(shí)，該單元正常工作“啟用”，產(chǎn)生指定的輸出（例如TTL）。當(dāng)引腳被禁止時(shí)，“邏輯0”（ex 0 Vdc）進(jìn)入高阻抗或三態(tài)模式。三態(tài)模式允許客戶從電路中移除石英振蕩器而無需將其物理移除。用于調(diào)整，測試或解決他們的電路板問題。
對稱性：信號處于邏輯高電平的每個(gè)周期的百分比。該參數(shù)在指定的電壓閾值或輸出波形幅度的百分比下測量。
英文版：
Aging: A systematic average change of an oscillator’s output frequency as a function only of time. Aging does not include effects of changing environments.
Deviation: The amount by which a quantity differs from its nominal value. For purposes, the amount by which a frequency differs from the nominal or specified frequency.
Enable/Disable: The enable/disable pin is similar to an on/off switch. A low or logic 0 on the enable/disable causes the unit not to oscillate. A “high” or logic 1 on the enable/disable pin allows the unit to work as normal (enabled) producing the specified output.
Fall Time: the time required for a signal to go from Logic ‘1’ to logic ‘0’.
Frequency Range: The range of frequencies over which an oscillator can be fabricated with minimal impact on specifications.
Linearity: The departure from a straight line relationship of control voltage to output frequency.
Oscillator: A circuit or device that produces an alternating current of a specific frequency at its output terminals.
Phase Noise: The ratio of the power density of one phase modulation sideband to the total signal. All phase noise data in the catalog are normalized to a one Hertz equivalent bandwidth.
Load (Fan out): The capacity of the oscillator to drive other devices. TTL devices are specified in the number of gates that can be driven; i.e., 10 TTL gates. CMOS outputs are specified in pF; i.e. 15 pF or 50 pF loads.
PPM: The abbreviation for “Parts Per Million,” a method of calculation used to specify the permissible
frequency deviation of a crystal or oscillator. May also be seen as “ppm”.
Pullability: The frequency shift of a VCXO as a function of control voltage.
Rise Time: The time required for a signal to go from Logic ‘0’ to logic ‘1’.
Stability: The change in oscillator frequency, referenced to the desired oscillator frequency, caused by temperature change.
Start-Up: The period from the instant voltage is applied to the oscillator until the oscillator output is stabilized.
Symmetry: The percentage of each period that a signal is in logic high. This parameter is measured at a specified voltage threshold or at a percentage of the output waveform amplitude.
Tri-state: The tri-state option is similar to the Enable/Disable. When you have a “logic 1” (ex 5 Vdc) on pin1,the unit works as normal “enabled” producing the specified output (ex TTL). When the pin is disabled, “logic 0” (ex 0 Vdc) it goes into high impedance or tristate mode. The tristate mode allows the customer to remove the oscillator from their circuit without physically removing it. Useful for tuning, testing or trouble shooting their board.
Warm-Up: The time required for an oscillator’s frequency to settle to within a given tolerance of the frequency several hours later.
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